ThreadX with IAR for A53

Hello kevin xiang,

We want to port threadx for A53 with IAR. There are not porting demo of IAR on GITHUB. It’s difficult writing assemble code for us. So does anyone have the example?

For porting ThreadX for Cortex-A53 with IAR you may check few examples for IAR on GitHub, which might help:

• ThreadX Cortex-A53 Examples: This GitHub repository contains examples for Cortex-A53, though they are tailored for ARM DS rather than IAR.
• Startup Code for Cortex-A53: This GitHub repository provides startup code and initialization for Cortex-A53, which might be useful for your porting efforts.

What's the different with A5x and A53/A55/A57, can we use the A5x IAR port example？

The ARM Cortex-A5x series generally refers to older architectures, while A53, A55, and A57 are part of the ARM Cortex-A family with specific enhancements:

• A53: Focuses on power efficiency and is widely used in mobile devices.
• A55: Offers improved performance and efficiency compared to A53, with better support for machine learning workloads.
• A57: Designed for high performance, often used in servers and high-end devices.

You can partially use the A5 IAR port example only if you're running A53/A55/A57 in 32-bit (AArch32) mode. If you're using 64-bit (AArch64) mode, then the A5 port might not work as expected.

Hope this helps. Thank you!

Hello kevin xiang,

Please refer brief explanation for this: Startup Code for Cortex-A53

The file startup.S from the ThreadX repository for Cortex-A53 provides the startup code for initializing the ARMv8-A architecture in AArch64 mode. The break down and analyze the key sections of this code.

Key Sections of startup.S

1. File Header and Includes:

// Armv8-A MPCore EL3 AArch64 Startup Code

// Basic Vectors, MMU, caches and GICv3 initialization

// Exits in EL1 AArch64

#include "v8_mmu.h"

#include "v8_system.h"

#include "GICv3_aliases.h"

This section includes necessary headers for MMU, system, and GICv3 initialization.

2. Global Declarations:

.section StartUp, "ax"`` ``   

.balign 4`` ``   

.global el1_vectors`` ``   

.global el2_vectors`` ``   

.global el3_vectors`` ``   

.global _start`` ``  

 .global MainApp

Here, global symbols are declared for vector tables and entry points.

3. Vector Base Address Register (VBAR) Initialization:

start64:        

ldr x1, =el1_vectors        

msr VBAR_EL1, x1        

ldr x1, =el2_vectors        

msr VBAR_EL2, x1        

ldr x1, =el3_vectors        

msr VBAR_EL3, x1

This code sets up the VBAR for different exception levels (EL1, EL2, EL3).

4. GICv3 Initialization:

msr SCR_EL3, xzr`` ``       

isb`` ``       

mov x0, #15`` ``       

msr ICC_SRE_EL3, x0`` ``       

isb`` ``       

msr ICC_SRE_EL1, x0`` ``       

msr ICC_SRE_EL2, x0

This section configures the Generic Interrupt Controller (GIC) to operate in GICv3 mode.

5. Exception Level Configuration:

mov x3, #(SCR_EL3_RW | SCR_EL3_SMD | SCR_EL3_NS)`` ``       

msr SCR_EL3, x3`` ``       

isb`` ``       

mov x2, #HCR_EL2_RW`` ``       

msr HCR_EL2, x2`` ``       

msr VTTBR_EL2, xzr

This code sets the exception levels as non-secure and configures the Hypervisor Control Register (HCR).

6. Branch to Main Application:

// Branch to thread start        

// B MainApp

Finally, the code branches to the main application entry point.

Detailed Analysis

• Vector Base Address Register (VBAR) Initialization: The VBAR is used to hold the base address of the vector table for handling exceptions. The code loads the addresses of the vector tables for EL1, EL2, and EL3 into the respective VBAR registers.
• GICv3 Initialization: The GICv3 initialization involves setting system register enables for all relevant exception levels and selecting the GICv3 operating mode. This ensures that the interrupt controller is properly configured to handle interrupts in the system.
• Exception Level Configuration: The SCR_EL3 register is configured to set lower exception levels as non-secure, with no access back to EL2 or EL3, and ensuring they are AArch64 capable. The HCR_EL2 register is set to allow EL1 to operate in AArch64 mode.
• Branch to Main Application: The final step is to branch to the main application entry point, which is typically where the main execution of the application begins.

Conclusion:

The startup.S file is crucial for setting up the initial environment for the Cortex-A53 processor, including vector tables, interrupt controller, and exception levels. Understanding this code is essential for ensuring that the system is correctly initialized and ready to execute the main application.

Hope this helps. Thank you!